1. Field of the Invention
The present invention relates generally to a method for manufacturing a circuit board with a buried element, and more specifically to a method for manufacturing a circuit board having a buried element including high density pin count and the circuit board structure having the buried element.
The so-called “embedded passives” generally indicate passive elements which are buried within multiple layers constituting a circuit board during the fabrication process. During the fabrication process of a circuit board, etching or screen printing techniques are implemented in order to directly form the passive elements, such as capacitor or resistor, on the inner layers which are later passed through the pressing and lamination processes to discrete the passive elements within the circuit board, thereby eliminating the soldering technique and effectively increase the mounting surface area for layout of circuits and the buried active and passive elements.
2. The Prior Arts
In the presently available circuit board with the buried passive elements, active elements can be also buried therein by implementing the above similar technique so as to increase the entire density of the elements. Since the functions of mobile phones of other electronic devices of present days become larger as days gone by, the I/O pin count of chips inherently should also be increased such that fabrication of a carrier plate requires reduced spacing among the I/O pins in order to form the high density pins. Since the I/O pin count of the chips used microvias to establish electrical communication among the circuit structure in the circuit board, it is highly desired to reduce the size of microvias and the spacing among the microvias so as to accommodate more buried elements in the circuit board.
The presently existing microvia is primarily manufactured by the laser drilling process such as conformal mask drilling, enlarge window drilling and copper direct drilling. FIG. 1 shows how a copper window is formed according to the prior art method. As illustrated, a first circuit 7a is formed on a first stack plate 1a. Next, the insulation layer 3a is formed on the first stack plate 1a and the first circuit 7a, and the second circuit 11a is formed on the insulation layer 3a. Then, part of the second circuit 11a is etched to form the opening (copper window 9a), and the opening is processed by the laser 16a to form the conduction hole 14a on the insulation layer 3a. 
However, the diameter of the conduction hole manufactured by the process of copper window is limited by the size of the laser beam passing through the mask, particularly the processes of photoresist development and photolithography. As a result, the size of the window for the conduction hole can not be further reduced and the circuit density of the circuit board is hard to increase, thereby hindering the conduction hole to establish electrical communication with the high density pin count of the active element.
Specifically, since it is difficult for a copper foil (the second circuit 11a) to absorb the laser wavelength, the process of photoresist development needs the help of the photolithography to form the opening in the second circuit 11a. Based on the current technology, the window formed on the patterned photoresist layer has a minimum size larger than 50 μm. Thus, the opening formed by etching the second circuit 11a is surely larger than 50 μm.
In addition, the process of desmear performed after laser drilling greatly widens the opening size such that the circuit spacing in the final product is only 140 μm.
In addition, the currently technique of mechanical drilling is done to form a through hole with a diameter 0.5˜3 mm for serving as a target point, the alignment tolerance and the International transfer tolerance is roughly 15 μm. Thus, the tolerance error on the drilled object is generally greater than 30 μm, which, in turn, limits the etching process done onto the circuits (or copper pads) and causes no width reduction in the circuits and no spacing reduction among the circuits (failing to provide more high density pin). If the copper window is further widened in the copper window process, the usage of the available circuit area of the second circuit 11a is reduced. While the process of direct laser may omit the process of forming the copper window, the absorption of the laser beam needs to increase and the size of the opening is still limited by the beam size through the mask.
Therefore, one drawback of the prior art method is that the opening size formed through the copper window process has a diameter greater than 50 μm, the circuit path spans more greater than 150 μm, the spacing between adjacent pair of the circuits is greater than 30 μm, which in turn, only accommodate chips with lesser pin counts. Owing to the preceding restrictions, the alignment tolerance and the International transfer tolerance, the size of microvia cannot be miniaturized so is the spacing among the circuits. Since the prior art method and structure is not suitable for burying the active element with high density pin count, a method for manufacturing a circuit board with buried element having high density pin count is urgently needed to overcome the above problems in the prior arts.